Yahoo My Yahoo Mail Welcome Guest Sign Out My Account Finance Home Help Home Investing Market Overview Market Stats Stocks Mutual Funds ETFs Bonds Options Industries Currency Education News Opinion Markets Investing Ideas Expert Advice Special Editions Company Finances Providers Personal Finance Banking Budgeting Career Work College Education Family Home Insurance Loans Real Estate Retirement Taxes How to Guides Tech Ticker Get Quotes Finance Search Press Release Source IBM IBM Builds World s Smallest SRAM Memory Cell Monday August am ET YORKTOWN HEIGHTS NY MARKET WIRE Aug IBM IBM News and its joint development partners AMD Freescale STMicroelectronics Toshiba and the College of Nanoscale Science and Engineering CNSE today announced the first working static random access memory SRAM for the nanometer nm technology node the world s first reported working cell built at its mm research facility in Albany NY. SRAM chips are precursors to more complex devices such as microprocess! ors. The SRAM cell utilizes a conventional six transistor design and has an area of . um breaking the previous SRAM scaling barriers. Researchers achieved this breakthrough at CNSE of the University at Albany State University of New York. CNSE s Albany NanoTech is the world s most advanced university based nanoelectronics research complex. IBM and its partners do much of their leading edge semiconductor research at CNSE. A nanometer is one one billionth of a meter or about times smaller than the width of a human hair. We are working at the ultimate edge of what is possible progressing toward advanced next generation semiconductor technologies said Dr. T.C. Chen vice president of Science and Technology IBM Research. This new development is a critical achievement in the pursuit to continually drive miniaturization in microelectronics. nm is two generations away in chip manufacturing. The next generation is nm where IBM and its partners are in development with their leading nm! high K metal gate technology that no other company or consortium can match. Traditionally an SRAM chip is made more dense by shrinking its basic building block often referred to as a cell. IBM alliance researchers optimized the SRAM cell design and circuit layout to improve stability and developed several novel fabrication processes in order to make the new SRAM cell possible. The researchers utilized high NA immersion lithography to print the aggressive pattern dimensions and densities and fabricated the parts in its a state of the art mm semiconductor research environment. SRAM cell size is a key technology metric in the semiconductor industry and this work demonstrates IBM and its partners continued leadership in cutting edge process technology. Key enablers of the SRAM cell include band edge high K metal gate stacks transistors with less than nm gate lengths thin spacers novel co implants advanced activation techniques extremely thin silicide and damascene copper contacts. Additional details of this achievement will be presented at the IE! EE International Electron Devices IEDM annual technical meeting to be held in San Francisco CA December . Contact CONTACT Michael Loughran IBM mloughraus.ibm.com . . cell . . Source IBM Email Story Set News Alert Print Story Copyright Yahoo Inc. All rights reserved. Privacy Policy Terms of Service Copyright Marketwire . All rights reserved. All the news releases provided by Marketwire are copyrighted. Any forms of copying other than an individual user s personal reference without express written permission is prohibited. Further distribution of these materials is strictly forbidden including but not limited to posting emailing faxing archiving in a public database redistributing via a computer network or in a printed form
Source: http://biz.yahoo.com/iw/080818/0425605.html
Read also car loan mistake
Subscribe to:
Post Comments (Atom)
No comments:
Post a Comment